Hello,
 
I try to run my own application (Hello.elf) inside a Linux system running on Ariane. The instantiation of Ariane and Linux was done according the description at the github page: https://github.com/pulp-platform/ariane.
 
According to this page https://github.com/pulp-platform/ariane-sdk/issues/25 the second partition on the SD card should be mounted at boot time, therefore, I just copied the binary into that partition. Unfortunately, I can't find the second partition.
 
During my search for a solution I found that Ariane repairs the GPT table of the SD card in such a way that fdisk detects the primary GPT table as corrupted, if the SD card is again inserted into my normal computer.
 
Below I post the output of fdisk before and after booting Linux on Ariane, as well as the part of the boot process, where the GPT is repaired.


Befor running Ariane (output at normal computer after running $ sudo sgdisk --clear --new=1:2048:67583 --new=2 --typecode=1:3000 --typecode=2:8300 /dev/sdb):
$ sudo fdisk -l /dev/sdb
Disk /dev/sdb: 29,7 GiB, 31914983424 bytes, 62333952 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: gpt
Disk identifier: B40F3443-EC5F-4185-8F91-C8E263A0DABA

Device     Start      End  Sectors  Size Type
/dev/sdb1   2048    67583    65536   32M ONIE boot
/dev/sdb2  67584 62333918 62266335 29,7G Linux filesystem

During the linux start on Ariane:
[   30.766351] GPT: Primary header thinks Alt. header is not at the end of the disk.
[   30.766351] GPT: Primary header thinks Alt. header is not at the end of the disk.
[   30.784484] GPT:62333951 != 62412799
[   30.784484] GPT:62333951 != 62412799
[   30.801305] GPT:Alternate GPT header not at the end of the disk.
[   30.801305] GPT:Alternate GPT header not at the end of the disk.
[   30.818495] GPT:62333951 != 62412799
[   30.818495] GPT:62333951 != 62412799
[   30.834014] GPT: Use GNU Parted to correct GPT errors.
[   30.834014] GPT: Use GNU Parted to correct GPT errors.
[   30.851527]  mmcblk0: p1 p2
[   30.851527]  mmcblk0: p1 p2

After running Ariane (output at normal computer)
$ sudo fdisk -l /dev/sdb
The primary GPT table is corrupt, but the backup appears OK, so that will be used.
Disk /dev/sdb: 29,7 GiB, 31914983424 bytes, 62333952 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: gpt
Disk identifier: B40F3443-EC5F-4185-8F91-C8E263A0DABA

Device     Start      End  Sectors  Size Type
/dev/sdb1   2048    67583    65536   32M ONIE boot
/dev/sdb2  67584 62333918 62266335 29,7G Linux filesystem

Any idea why the second partition is not recognised? Or more precisely, why the GPT table gets corrupted?


Thanks,
Jakob

Hi,
I am trying to use pulp-riscv-gnu-toolchain for Ibex (formerly Zero-riscy). The provided multi-lib covers rv32-ec and rv32-imc but rv32-ic and rc32-emc configurations are missing. I tried to build the toolchain specifically for these two configurations but so far with no success:

For rv32-ic I used:
./configure --prefix=... --with-arch=rv32ic --with-abi=ilp32 --with-cmodel=medlow
It compiled successfully, however the generated "libgcc.a" contained "mul" operations that resulted in "invalid instruction error" during RTL simulation.


For rv32-emc I used:
./configure --prefix=... --with-arch=rv32emc --with-abi=ilp32 --with-cmodel=medlow
The compilation failed:
--with-arch=rv32emc is not supported.  The argument must begin with rv32i, rv32g, rv64i, or rv64g.

Is there a way to compile for rv32-ic and rv32-emc?

Thanks and regards,
Mehrdad

Hello,

I am currently trying to implement a HWPE into the PULPissimo platform.
Now i am facing a few problems and it would be great if someone could help me clarify some things.
This might be a rather long thread with quite a few questions but i hope that this will not only help me but also other people that (might) face the same or similar problems as i do.

What i am trying to do to understand the interaction between the L2 Memory, the TCDM interconnect and a HWPE, is to make my own simple HWPE.
At first it should only consist of a couple of registers and be able to read/write from/to the L2 Memory.
This means that data flow is the thing i am interested in at the moment.
If this simple HWPE works and can successfully read/write then a more complex HWPE can easily follow.


So first i was reading the HWPE Interface Specifications and the Systemverilog code to get a rough overview of the (possible) interactions between L2 Memory <-> TCDM <-> HWPE.
This is how i think things are working so please correct me if i am wrong:


There are (at least) two components that can do read/write operations on the L2 Memory.

First the core which has an instruction memory interface and a data memory interface.
The fc_subsystem has two XBAR_TCDM_BUS.Master ports used by the core.
One for data (l2_data_master) and one for instructions (l2_instr_master).
These connect the core with the XBAR_TCDM_BUS.Slave ports of the soc_interconnect_wrap.
The soc_interconnect itself then has a RISC data port and a RISC instruction port.
Now this is where things start to get more confusing to me.
But the important thing is that the core can use its data memory interface to interact with the L2 Memory.
This means i know that it is possible to send signals to the L2 Memory (req, addr, etc.) for read/write operations.
So one possibility would be to have the HWPE interact with the L2 Memory the same way the core does.
This brings up some question:
1) Can the core and the HWPE share the same bus? If yes, would that mean that the core would have to stall if the HWPE is using the bus?
2) If they don't share the same bus and you create a new connection to the L2 Memory based on the cores data memory interface, how could you handle possible errors regarding Write-After-Read, etc. I am not sure if the request/response trees are able to handle such scenarios as PULPissimo is a single core system. Then again there are also multi-core variants but i haven't read anything about data flow in such PULP systems.
3) Similar to 2) but this time the HWPE would use more than one port (similar to how the current HWPE implementation works).

The second component that can do read/write operations on the L2 Memory is the HWPE.
At least in the pulp-rt-example the data is loaded into the L2 Memory.
Now the HWPE uses streams and i tried to make my own HWPE use only one master port.
Questions regarding the HWPE variant:
1) Can you use a single port for read/write or do you need at least two (source+sink)?
2) I tried the pulp-rt-example for the accelerator and reduced the number of master ports down to two. This failed as it seems just changing the parameters for the number of master ports is not enough. You probably have to do some changes in the stream controller, right? (maybe even more changes)


So in a nutshell: I am trying to implement my own HWPE in a PULPissimo platform. Currently the HWPE should only be able to read/write from/to the L2 Memory. At first i wanted to use only one port for that. If that works i wanted to increase the number of ports.
The questions are:
- Does it make sense to use the same port as the core?
- Does it make sense to create a new port which mimics the port of the core?
- Would the best/easiest/most efficient way be to just use the ports of the HWPE which are already defined and just replace the example HWPE with my own?
- What are the limits of the number of ports for both the core style variant as well as the HWPE variant?


If anything is unclear please feel free to ask and i will try my best to give further details.


Thank you very much.
LPLA

Hello,

I am trying to build RTL simulation platform for pulpissimo and for the command "make clean lib build opts", I am getting the following error.

Modifying /root/altera/16.0/modelsim_
ase/linuxaloem/../modelsim.ini
Building L2_tcdm_hybrid_interco/soc_interconnect
Building adv_dbg_if/adv_dbg_if
Building apb2per/apb2per
Building apb_adv_timer/apb_adv_timer
Building apb_fll_if/apb_fll_if
Building apb_gpio/apb_gpio
Building apb_node/apb_node
Building apb_interrupt_cntrl/apb_interrupt_cntrl
Building axi_node/axi_node
Building axi_slice/axi_slice
Building axi_slice_dc/axi_slice_dc
Building axi_mem_if/axi_mem_if
Building timer_unit/timer_unit
Building common_cells/common_cells_all
** Error: ../ips/common_cells/src/id_queue.sv(268): Questa has encountered an unexpected internal error: ../../src/vlog/vgentd.c(515). Please contact Questa support at http://supportnet.mentor.com/
/root/pulp-sdk/pulpissimo/sim/vcompile//ips/common_cells.mk:73: recipe for target '/root/pulp-sdk/pulpissimo/sim/modelsim_libs/common_cells_lib/common_cells_all.vmake' failed
make[2]: *** [/root/pulp-sdk/pulpissimo/sim/modelsim_libs/common_cells_lib/common_cells_all.vmake] Error 2
/root/pulp-sdk/pulpissimo/sim//vcompile/ips.mk:14: recipe for target 'build' failed
make[1]: *** [build] Error 2
Makefile:33: recipe for target 'build' failed
make: *** [build] Error 2

Can you please tell me how to rectify this?

Thanks and Regards
Hithaishi

Hello.

In Pulpissimo, there are 2 JTAG modules - dmi_jtag, dm_top / jtag_tap_top & lint_jtag_wrap (pulp_soc.sv).

I guess dmi_jtag & dm_top are from RISC-V Debug Specification,
and jtag_tap_top & lint_jtag_wrap are sub-module of adv_dbg_if.

In Pulpino, zero-riscy core, whose registers are memory-mapped, uses adv_dbg_if as a debug module.
But ibex core at Pulpissimo follows the RISC-V Debug Specification and has no debug interface except one bit debug signal.


So, I don't know why lint_jtag_wrap still necessary in Pulpissimo.
(Any limitations for dm_top to access system bus ??)


Thanks.

Hello All...

I have been trying to install PULPissimo. I have installed all the dependencies and now im working on building RTL simulation platform. For the command "make clean lib build opts" i'm getting the following errors 

/bin/bash: vlib: command not found
vcompile/build.mk:56: recipe for target '/root/pulp-sdk/pulpissimo/sim/modelsim_libs/L2_tcdm_hybrid_interco_lib' failed
make[2]: *** [/root/pulp-sdk/pulpissimo/sim/modelsim_libs/L2_tcdm_hybrid_interco_lib] Error 127
/root/pulp-sdk/pulpissimo/sim//vcompile/ips.mk:53: recipe for target 'lib' failed
make[1]: *** [lib] Error 2
Makefile:37: recipe for target 'lib' failed
make: *** [lib] Error 2


Can i know what to do next ?


Thanks and Regards
Hithaishi

Hello..
I have been trying to install PULPissimo and the GNU Compiler tool chain was  built successfully. in the PULP- Builder installation i have installed all the dependencies and the GVsoC build was built. But, in the "Runtime Build" process im facing an error for the command 

Hello...
I'm Shilpa. As a part of my academic project I'm installing PULPissimo Platform for executing the RTL simulation. I found this platform very interesting and I was very keen to know about it in detail. But, during the installation process I'm facing certain errors which as a starter I'm unable to rectify. So, is there any basic procedures or guidance that can be provided.
Thank you

Hello,

We have been trying to understand how the Pulpissimo memory map is generated.
Our purpose is to add our own modules (ultra low power memory) to it and we would need to understand it.

We found that memories are defined in l2_ram_multi_bank.sv, but how to add new memory to it?

Please, can you clarify file names that need to be modified to change Pulpissimo memory map?

Br,
Akim

I can see that there is no Issues panel in pulp-sdk project on GitHub. I have some things to discuss regarding Ibex integration and I guess it would be much better place for this than this forum. In my opinion reliable SDK is one of the most important parts of the entire system, so maybe it would be nice idea to enable it for others to easily file issues and ask questions?