Hello,

I am trying to build RTL simulation platform for pulpissimo and for the command "make clean lib build opts", I am getting the following error.

Modifying /root/altera/16.0/modelsim_
ase/linuxaloem/../modelsim.ini
Building L2_tcdm_hybrid_interco/soc_interconnect
Building adv_dbg_if/adv_dbg_if
Building apb2per/apb2per
Building apb_adv_timer/apb_adv_timer
Building apb_fll_if/apb_fll_if
Building apb_gpio/apb_gpio
Building apb_node/apb_node
Building apb_interrupt_cntrl/apb_interrupt_cntrl
Building axi_node/axi_node
Building axi_slice/axi_slice
Building axi_slice_dc/axi_slice_dc
Building axi_mem_if/axi_mem_if
Building timer_unit/timer_unit
Building common_cells/common_cells_all
** Error: ../ips/common_cells/src/id_queue.sv(268): Questa has encountered an unexpected internal error: ../../src/vlog/vgentd.c(515). Please contact Questa support at http://supportnet.mentor.com/
/root/pulp-sdk/pulpissimo/sim/vcompile//ips/common_cells.mk:73: recipe for target '/root/pulp-sdk/pulpissimo/sim/modelsim_libs/common_cells_lib/common_cells_all.vmake' failed
make[2]: *** [/root/pulp-sdk/pulpissimo/sim/modelsim_libs/common_cells_lib/common_cells_all.vmake] Error 2
/root/pulp-sdk/pulpissimo/sim//vcompile/ips.mk:14: recipe for target 'build' failed
make[1]: *** [build] Error 2
Makefile:33: recipe for target 'build' failed
make: *** [build] Error 2

Can you please tell me how to rectify this?

Thanks and Regards
Hithaishi

Hello.

In Pulpissimo, there are 2 JTAG modules - dmi_jtag, dm_top / jtag_tap_top & lint_jtag_wrap (pulp_soc.sv).

I guess dmi_jtag & dm_top are from RISC-V Debug Specification,
and jtag_tap_top & lint_jtag_wrap are sub-module of adv_dbg_if.

In Pulpino, zero-riscy core, whose registers are memory-mapped, uses adv_dbg_if as a debug module.
But ibex core at Pulpissimo follows the RISC-V Debug Specification and has no debug interface except one bit debug signal.


So, I don't know why lint_jtag_wrap still necessary in Pulpissimo.
(Any limitations for dm_top to access system bus ??)


Thanks.

Hello All...

I have been trying to install PULPissimo. I have installed all the dependencies and now im working on building RTL simulation platform. For the command "make clean lib build opts" i'm getting the following errors 

/bin/bash: vlib: command not found
vcompile/build.mk:56: recipe for target '/root/pulp-sdk/pulpissimo/sim/modelsim_libs/L2_tcdm_hybrid_interco_lib' failed
make[2]: *** [/root/pulp-sdk/pulpissimo/sim/modelsim_libs/L2_tcdm_hybrid_interco_lib] Error 127
/root/pulp-sdk/pulpissimo/sim//vcompile/ips.mk:53: recipe for target 'lib' failed
make[1]: *** [lib] Error 2
Makefile:37: recipe for target 'lib' failed
make: *** [lib] Error 2


Can i know what to do next ?


Thanks and Regards
Hithaishi

Hello..
I have been trying to install PULPissimo and the GNU Compiler tool chain was  built successfully. in the PULP- Builder installation i have installed all the dependencies and the GVsoC build was built. But, in the "Runtime Build" process im facing an error for the command 

Hello...
I'm Shilpa. As a part of my academic project I'm installing PULPissimo Platform for executing the RTL simulation. I found this platform very interesting and I was very keen to know about it in detail. But, during the installation process I'm facing certain errors which as a starter I'm unable to rectify. So, is there any basic procedures or guidance that can be provided.
Thank you

Hello,

We have been trying to understand how the Pulpissimo memory map is generated.
Our purpose is to add our own modules (ultra low power memory) to it and we would need to understand it.

We found that memories are defined in l2_ram_multi_bank.sv, but how to add new memory to it?

Please, can you clarify file names that need to be modified to change Pulpissimo memory map?

Br,
Akim

I can see that there is no Issues panel in pulp-sdk project on GitHub. I have some things to discuss regarding Ibex integration and I guess it would be much better place for this than this forum. In my opinion reliable SDK is one of the most important parts of the entire system, so maybe it would be nice idea to enable it for others to easily file issues and ask questions?

Hi, is there somewhere a guide how to create new SoC configuration for pulp-sdk? I'm basing on PULPissimo and just copied some files in `pulp-configs` to create custom configuration. I wonder though if there is some kind of recommended way of doing this and if there is some sort of documentation anywhere. I've seen different scripts (`pulp_chip_gen`, `pulp_soc_gen`, …), but there is no description which does what and in what scenarios one should be used.

Hi,
I would like to do some manipulation of the user and general purchase I/Os of the pianissimo platform, for example to light up a user LED via pressing down a pushbutton.
I found the functions in the sdk runtime doc for configuring the gpio as a bus such as rt_gpio_init and rt_gpio_pin_configure etc, but I did not find any document mentioning the exact address/pin or registers that are corresponding to the LEDs or pushbuttons. I am wondering where to get the detailed info of such so that I can light up a user LED?

Thanks,
Mapletree

Hi,
I have generated a Pulpissimo platform bitstream for Xilinx ZCU102 board. Now I am at the stage to compile a "hello world" example to try on the FPGA. I am having two problems here:

1. On the pulpissimo web page, after the instructions on how to create the .c file that includes the baudrate and frequency of the UART and the main() function, it gives instructions on how to compile an application by issuing " make clean all" command, but there is no corresponding Makefile, therefore, I got an error " No targets specified and no makefile found". I did all these in pulp-builder home directory. My questions are: a). is there an existing Makefile that I can borrow to compile my hello.c for RISCV?  b).  If I need to create my own Makefile, do I need to include the boot code? if so where to get the boot code (the same code in sim/boot directory)? It will be nice if there is an example Makefile that I can start with.

2. When I tried to connect to the JTAG interface on the board(JTAG pins are allocated on PMOD) by issuing the openocd command, I got an error saying "embeddedtartup.tcl:21:Error: Unknown target type riscv". The command I issued: $openocd -f openocd-zcu102-digilent-jtag-hs2.cfg. The screenshot of the error massage and the openocd config file are attached.


Please help!

Thanks,
Mapletree

Attached Files

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  openocd-zcu102-digilent-jtag-hs2.txt (Size: 667 bytes / Downloads: 3)