Hello again,

I'm trying to build hero-sdk, specifically hero-gcc-toolchain, for use on a ZCU102 and I'm running into some errors.
The first error is when compiling aeabi_lcsts.c:

Hi,

Can you help me resolve this Busybox version issue?

Hello there,

I currently collect information for my bachelor thesis and want to compare popular RISC-V implementations.
You have a nice graphic 


Does there exist a documentation or has somebody knowledge about how the RISC-V cores match to for example ARM cores.
For example:

RI5CY <-> ARM cortex M0
or
PULPino <-> ARM cortex M0

Greetings from Munich,

Aaron

Edit:
The people over at Si-Five compare their cores here for example https://www.sifive.com/core-designer (scroll to the bottom)

I am getting the error at the time of compilation when iI use -march=RV64.
Even i tried with the rv32 or rv64 also.

Regards
Karthik

I have been trying to migrate PULPino project to Vivado 2018.1 workflow. I have been successfully able to compile hardware-software project to obtain files in sd_image. Setting up and booting the SD Card sets up Programmable Logic (as indicated by blue light). Linux is NOT booting. Please help me identify and fix the problem.

Hello,

I'm building the hero-sdk as per the github instructions but it's failing at the pulp-sdk stage.
Actually I'm trying on 2 systems, Debian 9.2 and Ubuntu 16.04.
Both have the same result and symptoms.
It looks like some files which should be copied from ./pulp-sdk/json-tools to ./pulp-sdk/build/sdk/json-tools are missing. I.E there's no Makefile so make doesn't know what to do.
Anybody on here have an idea what's going wrong?

Hi,

I noticed that Google IPU team reported serveral bugs about RI5CY core in the RISC-V Workshop this MAY. I am wondering whether PULP team has yet fixed them in the Github release.

Hope for your response.

----- Details about the bugs -----
Bugs found in:
○ Multiplier
○ LSU

Bugs reported in page 12 of  Google's Reports on the evaluation of RI5CY
RISC-V Workshop website: RISC-V Workshop in Barcelona Proceedings
RTL Core for RI5CY Github release

I'd like to ask is there any UVM environment created for PULPINO SOC, or even for one of the following cores:
  1- RI5CY
  2- Zero-riscy

Thanks 

Hi,
I'm trying to use the I2C controller to communicate with my own I2C peripheral. First, I was trying to build the tb by including the I2C EEPROM (I've followed the README instructions). The problem is that, when using the example program for I2C, the RTL simulation gets stuck at the first write operation. Moreover, SDA and SCL signals never toggle during RTL simulation.

Do you have an example program I can use to make I2C work? I guess I need to make some initialization..

Hi, 

I'm trying to preload the program in L2 cache but i'm unable to trace which addresses goes into which memory
so far what i got tracing is the hello world example:

/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/bank_sram24k_scm8k_pri0_i/cut_0/MEM
addresses in stimuli file from 1C000000 - 1C001030 go in this memory

/tb_pulp/i_dut/soc_domain_i/pulp_soc_i/l2_ram_i/bank_sram_pri1_i/MEM
 address in stimuli file from 1C008000 - 1C00AF80 go in this memory

but i have no idea where the rest goes. 
Question 1: is the mapping mentioned anywhere in the hdl files?
Question 2: I've not been able to build the documents in ipstools due to python libraries errors is there a pdf or a latex version i can get anywhere else online?

Thanks,
Bassma