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| I2C cannot write to TX_SADDR |
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Posted by: nikolas - 03-03-2021, 11:07 AM - Forum: PULP General questions
- Replies (2)
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Hey everyone
I am trying to set up an I2C on my NEXYS 4 board without using the rt api from the sdk.
Now I think I have understood the way how the uDMA works an I am also able to transmitt something over the I2C (clock is there and a signal on the SDA is there too), but this are
not the data I wanted to transfer.
My main problem now is, I am not able to write the address of my TX buffer to the TX_SADDR register. In the manual I can see that the TX_SADDR should be a read/write register but writing to it seams not be possible.
Does someone know what the problem could be or is there maybe an example how to setup peripherals connected to the uDMA without the help of the rt api?
Would really appreciate your help.
Thank you very much and have a nice day.
Code: //in a headerfile called pulpissimo.h
#define I2C0_RX_SADDR (*((volatile uint32_t *)0x1A102180))
#define I2C0_RX_SIZE (*((volatile uint32_t *)0x1A102184))
#define I2C0_RX_CFG (*((volatile uint32_t *)0x1A102188))
#define I2C0_TX_SADDR (*((volatile uint32_t *)0x1A102190))
#define I2C0_TX_SIZE (*((volatile uint32_t *)0x1A102194))
#define I2C0_TX_CFG (*((volatile uint32_t *)0x1A102198))
//in hal_i2c.c
__attribute__((section(".l2_data"))) uint8_t tx_buff[BUFFERSIZE];
__attribute__((section(".l2_data"))) uint8_t rx_buff[BUFFERSIZE];
__attribute__((section(".l2_data"))) uint8_t cmd_buff[BUFFERSIZE];
//in an initialisation function in hal_i2c.c
I2C0_RX_SADDR |= (uint32_t)&rx_buff[0]; //after this there is 0x00000000 in the register
I2C0_RX_SIZE |= BUFFERSIZE; //after this there is 0x00000000 in the register
I2C0_TX_SADDR |= (uint32_t)&tx_buff[0]; //after this there is 0x00000000 in the register
I2C0_TX_SIZE |= BUFFERSIZE; //after this there is 0x00000000 in the register
I2C0_CMD_SADDR |= (uint32_t)&cmd_buff[0]; //after this there is 0x00000000 in the register
I2C0_CMD_SIZE |= BUFFERSIZE; //after this there is 0x00000000 in the register
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| PULPino or PULPismo ? for a low-power microcontroller |
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Posted by: sit-vlsi - 02-28-2021, 03:01 PM - Forum: PULP General questions
- Replies (4)
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Hello, We are trying to design a ultra low-power microcontroller for IoT applications in a 0.18um CMOS technology and I am trying to decide to choose the PULPino or PULPismo platform.
PULPino seems like the more matured platform but PULPismo seems to be the replacement for PULPino.
Our core strength is analog so we want a platform which has a well-supported toolchain, etc.
So any advice on this topic will be greatly appreciated.
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| how to simulate CV32E40P core |
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Posted by: gsaitejareddy - 02-08-2021, 08:11 AM - Forum: PULP General questions
- Replies (2)
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Hi,
I am trying to simulate CV32E40P core. In example_tb file in core folder there is a make file. It is showing error
vlib-"10.7b" work
/bin/sh: 1: vlib-10.7b: not found
make: *** [Makefile:87: .lib-rtl] Error 127
I read in the documentation that there is a separate repository for verification. I have run the makefile in core-v-verif/cv32/sim/core. i was able to run hello world program. But i dont why in CV32E40P core it was not running.
I wanted to explore floating point unit in CV32E40P core. Can you please say how to simulate with system verilog files
I am not able to understand how to give input to the core. Please help me
Thanks in advance
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| Question about bitstream generation |
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Posted by: zorrolee777 - 02-04-2021, 06:24 PM - Forum: PULP General questions
- Replies (4)
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Hi, I'm new to this and got some errors when generating the bitstream file.
The code I ran:
Code: $ cd $COREVMCU/fpga
$ make clean_nexys rev=nexysA7-100T
$ make nexys rev=nexysA7-100T
Code: ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:48]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_slow_clk_gen' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:24]
ERROR: [Synth 8-6156] failed synthesizing module 'safe_domain' [/home/core-v-mcu/rtl/pulpissimo/safe_domain.sv:12]
ERROR: [Synth 8-6156] failed synthesizing module 'pulpissimo' [/home/core-v-mcu/rtl/pulpissimo/pulpissimo.sv:13]
ERROR: [Synth 8-6156] failed synthesizing module 'xilinx_pulpissimo' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v:22]
When I commented out the module, some other errors would come out, saying those modules are not found. I guess there're four of them, which are xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. I'm not sure if those modules are supposed to be generated by myself, or where should I get and put them? Any comments would be appreciated. Thanks in advance!
Sincerely,
Zorro
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| Compiling for RISCY without FP? |
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Posted by: LarsKeuninckx - 01-27-2021, 10:56 AM - Forum: PULP General questions
- Replies (2)
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I successfully got Pulpissimo with RISCY working on the Digilent ARTY-A7-100T board, running the "Hello" example using the pulp-SDK. Yeeey! 
I configured RISCY to not use a floating point unit, by setting:
Code: localparam USE_FPU = 0;
in xilinx_pulpissimo.v.
However, the gcc commands of the "Hello" example, following "make clean all", contain:
Code: ... -march=rv32imfcxpulpv2 -mfdiv ...
So the questions are:
- Does this mean floating point instructions are potentially still being generated?
- If so, how do I make the toolchain aware that RISCY was configured without FP unit?
Additional info: the toolchain was setup using the instructions at https://github.com/pulp-platform/pulp-ri...ation-pulp.
Thanks!
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| Failed at building the RTL simulation platform |
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Posted by: Jackie Zhang - 01-25-2021, 11:58 AM - Forum: PULP General questions
- Replies (4)
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Hi, All:
I followed the instruction to setup a simple run environment, but always failed at the build stage, with following messages:
** Error: ../ips/pulp_soc/rtl/pulp_soc/soc_interconnect.sv(22): Cannot find `include file "axi/assign.svh" in directories:
../ips/pulp_soc/../../rtl/includes, ../ips/pulp_soc/rtl/include, ../ips/pulp_soc/../axi/axi/include, /eda/Mentor/Questa10.7/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src, /eda/Mentor/Questa10.7/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src
I checked all cloned files, found AXI, dm, ... etc, NOT downloaded.
Could you someone help me on this issue?
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