Hello,

I'm new to using the PULP environment and currently I am trying to familiarize myself with the HERO platform implemented on my ZC706 board and I have a few questions:

• I saw that with OpenMP the workload to execute is sent to the cluster with 8 RISC-V cores.
However, can I choose precisely which cores will be used to run a workload ?
For example, I would like the workload W1 to be executed by cores PE0, PE1 and PE2 and the workload W2 to be executed by cores PE M to PE N-1.

• I suppose it is possible with the ZC706 FPGA board to have 2 clusters of 4 RISC-V cores.
Similar to the previous question, can I choose which cluster will run a workload ?

• I saw in the file "fe/rtl/includes/pulp_soc_defines.sv" on Github that it is possible to define an FPU. But I can't find the apu_package.sv file mentioned in the comment on line 45 to add an FPU.
Is it possible to add an FPU in big-pulp?
Is the FPU shared between the cores or is it one FPU per core ?

• Last question, Is it possible to add a HWCE to a cluster ?


Thanks in advance

Hi,

I have build the PULP RISC-V GNU Compiler Toolchain [1] with multilib. It contains the following targets:

• march=rv32ic, mreg=16:
  This is used for Micro-riscy. What is the difference compared to march=rv32ec of RISC-V GNU Compiler Toolchain [3]?
  
• march=rv32imfcxpulpv2:
  Is this rv32imfc plus the extra instructions introduced in RI5CY? (e.g. hw loops)
  
• march=rv32imcxpulpslim:
  What is this? I saw it has been used for zero-riscy [4]. What is the difference to rv32imc or rv32emc?
  

How are ARA open source going?



Best Regard,
Roy

I'm trying to simulate standalone booting from flash using the bootsel=0 and the bootrom.
What are the steps to prepare an image starting from the compiled elf file?
Do I just need to load it as is in the flash model for simulation, or are there some additional steps required?

Is there some documentation regarding this topic?

Thanks !

Hi,

I'm trying certain software debug tool on pulpissimo. To build alignment between source code and disassembly, I need to trace both "pc" and the corresponding "instruction" in the design during runtime.
I've found the "pc" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.pc_id_i[31:0]"
And probably the "inst" shall be "tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.instr[31:0]"

For example, on "hello" case, a piece of disassembly is:
   

The waveform is like:
   

you can see when the instruction is 32bit, disassembly is matched with waveform (eg. pc=0x1c008130, inst=0x82f72a23)
But when the instruction is 16bit, looks like I can find a signal in waveform to show the 16bit instruction correctly... for example, pc=0x1c008134, disassembly shows the instruction val=0xc69c; but the 32bit "inst" signal shows different value in the waveform...
Instead, I find the 16bit inst at output of L2 ram... But I can't use the output of L2 ram in my tool since it's too hard to align with pc...

any ideas?

Thank you!

Hello,

Right now I am trying to run the accelerator example on the zedboard, but right now I have a issue regarding of running the application. For some reason after this line of code __rt_periph_wait_event(ARCHI_SOC_EVENT_FCHWPE0, 1), the application loops. What can be a good approach to fix it?

Hi,

I migrated pulpissimo simulation env to a synthesizable env. I removed tb part so there is no JTAG action (but I confirmed the clocks are all fine in the system). bootsel has been set to 1'b1.
Even without the JTAG action, I expect at least boot-code can run correctly.
But, via compare PC (tb_pulp.i_dut.soc_domain_i.pulp_soc_i.fc_subsystem_i.FC_CORE.lFC_CORE.id_stage_i.pc_id_i[31:0]) value in golden simulation and my simulation. I found that after several instructions, my simulation jumped to another branch, like:
golden sim: .... 0x1a0002dc -> 0x1a0002de -> 0x1a0002e0 -> 0x1a0002e4 -> 0x1a0002e6 -> 0x1a000316 -> .....
my sim:      .... 0x1a0002dc -> 0x1a0002de -> 0x1a0002e0 -> 0x1a0002e4 -> 0x1a0002e6 -> 0x1a0002e8 -> .....
before that, the PC value and sequence is exactly the same

Now my problem of debugging it is: ./sim/boot/boot_code.cde is already made as hex file. I can find the src boot-code at https://github.com/pulp-platform/boot-code, but when I try to make executable, it is invoking "pulp-runtime/install/rules/pulp_properties.mk" but it's not there... (I want to make exe and then objdump it to debug with disassembly)

Can you please point me how to generate the corresponding disassembly to boot_code.cde? Or can you simply help me figure out why my simulation fails with the PC sequence I provided? 

Thank you!

I downloaded pulp riscv gnu toolchain and pulp sdk. I there a way to add a custom instruction to the riscv cross compiler?

Hi
I want to run simple hello.c example So I compiled as following:
riscv64-unknown-elf-gcc hello.c -L linker.lds -o hello.elf
where linker.lds is :

Hi,
I've already run "Hello" case successfully with Xcelium, now I have some further questions:
1. In readme I see it says "Either the RI5CY core or the Ibex one as main core". So by default, if I've built everything following readme, which core is used in the Soc?
2. In ARM cores, there is usually a program counter (PC) register, so that users can simply know where the issue happens (with disassembly code). Is there the similar register in Pulpissimo?
3. I see ./sim/boot/boot_code.cde is loaded in boot_rom. Is this boot_code.cde necessary for all the cases? Via the waveform of "Hello" case, I see something is read from boot_rom, but i'm not sure if the boot code is really used or not. What does the boot code do? Initialize the SoC? If I put my executable in SPI flash, can I still reuse the boot code before jumping to SPI content?