I read this interesting article- I do not know if this is an Ariane-like linux-capable core, but I am much more fascinated at its power efficiency at 1Ghz (or lower) than its 5ghz capabilities.
"Micro Magic details its 1GHz RISC-V processor core that consumes just 10mW when operated in the voltage-threshold region at 350mV.
Micro Magic in Sunnyvale, California, has already claimed that its RISC-V processor design was the fastest, but in an interview with eeNews Europe Mark Santoro, CEO of Micro Magic, said the processor core had also been designed so that it can operate down to at least 350mV, near the threshold voltage of the manufacturing process. "
"...However, the company has declined to say what manufacturing process or foundry manufacturer has been used. The company has said the design uses a FinFET process and that it examined physical design kits (PDKs) from three leading foundries seeking the broadest compatability before selecting one for manufacturing. The process is likely to be somewhere between 20nm and 10nm and from one of Globalfoundries, Samsung, SMIC and TSMC."
What is the correct way to add assembly files (.s) to a project compiled with the Makefile system in the SDK?
Adding them to PULP_APP_FC_SRCS leads to strange errors.
"We provide a simple runtime and a full featured runtime for PULPissimo. We recommend you try out first the minimal runtime and when you hit its limitations you can try the full runtime by installing the SDK."
1. What exactly are the limitations of the "simple runtime" vs the "full runtime SDK"? When to use which one?
2. How do you switch between the simple runtime and full runtime SDK? What is the proper way to uninstall the SDK? Just delete the pulp-sdk folder and git clone again?
Out of curiosity, I'm learning more about the RI5CY core, especially the ex_stage. I read the Near-Threshold RISC-VCore With DSP Extensions for Scalable IoT Endpoint Devices paper and I got the core from the dedicated github page. Using Synopsys Design Compiler and the 28nm FD-SOI technology (the only technology available to me), I synthesized the multiplier (mult.sv) present in the RI5CY core. I obtain a maximum operating frequency of the multiplier of 200 MHz.
This frequency seems to me a little low. Considering the various documents I have seen on the internet, I would expect to obtain a frequency rather between 450 and 650 MHz.
Does anyone know if the maximum frequency of 200MHz is actually too low for the RI5CY core multiplier?
I am exploring the various pros and cons to adapting 32-bit cores Ibex & CV32E40P to run μClinux (w/o MMU). If the power efficiency is not much less, I can understand the benefits of using CVA6 which can run full-featured (MMU) linux, but I am curious what the power consumption is for CVA6- I do not have access to the paper: "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications."
However I did read, "Micro-riscy is 1.6× smaller than Zero-riscy (∼11.6 kgates in UMC 65nm), has a power envelope of just 100μW at 160MHz and it is 1.4× more energy efficient than Zero-riscy on pure control code."
I would also like access to: "Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices" In a low-power 28-nm FD-SOI process, a peak efficiency of 193 MOPS/mW (40 MHz and 1 mW) can be achieved."
From reading the abstract, it appears Ibex can run at 100uW, and another core, in the 2nd article, runs at 1mW- Is that CV32E40P?
The reason I am asking is, I would like to build upon a research paper, the "Battery-Free Game Boy" in Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies September 2020 Article No.: 111, which uses an Ambiq Micro Apollo3 board running at sub-threshold voltage, similar to the near-threshold voltage of the RISC-V Core mentioned above. The theory is, if μClinux could be adapted to run on Ibex or CV32E40P, using external memory for RAM, an iPod, android phone, or even a laptop could be built with it and be powered by amorphous solar panels, and ultra-low power e-ink, with battery backup. Thank you.
Hello,
I'm currently trying to set up a Pulpissimo IP Core which can be used with Vivado IP Integrator to fasten the integration of AXI peripherals. I managed so far to route the AXI slave channels to the TL domain where I added corresponding pads which can be used to create an AXI AMBA interface. As the slave interface uses a 64-bit data channel I'm going to use Xilinx data converter IP to get a 32-bit data channel. What I'm missing at the moment is AXI clock and reset channels.
My question therefore is if the cluster clock would be suitable to use it, if there is already a dedicated AXI clock or reset, or if a dedicated clock divider for AXI has to be integrated. In the last case the question would be where to get a suitable clock signal.
Any is appreciated.
Regards,
Frankie
I have a question about the interrupt handling of a PULPissimo with a RI5CY core.
The thing is, I am able to generate timer interrupts as long as I use the rt_api.h file and the functions, that are implemented there. Everything works fine then.
It would be very nice now, if it is possible to write my own functions. So I took the PULPissimo datasheet and started to set the right registers.
For testing reasons I want to generate interrupts from one of the APB Timers, jump into a callback function and toggle an LED. But that does not happen.
The program jumps once into the callback function but after never again. If I debug and set a breakpoint in the callback function, this breakpoint will never be reached twice.
Also tested the timer if everything works there as expected and it looks like the timer is fine. And in the interrupt pending register the correct bit is set but it does not jump.
My question now is, is there something else, maybe an other register or something, that I have to clear or set? Maybe I did not understand the interrupt handling right?
Would be nice if someone can help me here.
Code:
/*=============================================================================================================================
* @file main.c
* @author
* @brief This is a testing program for the PULPissimo microcontroller that is implemented on a FPGA NEXYS4 board.
* There is a hardware abstraction layer, that was created for that board. This program helps to find out
* if everything is working as expected.
* @date 2021-01-02
* @version v1.0
============================================================================================================================*/
//#include <stdio.h>
#include <stdint.h>
#include "HAL/hal_gpio.h"
#include "HAL/HAL_Defines.h"
#include "HAL/hal_timer.h"
#include "HAL/hal_interrupt.h"
#include "HAL/pulpissimo.h"
//#include <rt/rt_api.h>
while(1)
{
//checks if timer is running as expected
if(TIM_CNT_LO >= 0xFFF)
hal_gpio_write(LED1, 1);
else
hal_gpio_write(LED1, 0);
}
return 0;
}
If it helps to understand my problem, here is the little test application I would like to run. The functions, that I wrote do not much more than setting the right bits of the right registers.
Thank you very much and wish you all a nice evening
I took a look at the Near-Threshold RISC-VCore With DSP Extensions for Scalable IoT Endpoint Devices paper.
At the Dotp-Unit side, there are two 17bx17b multipliers and four 9bx9b multipliers respectively the input operands are 16b and 8b. The support of signed operations is achieved by adding a sign bit to each input operand.
The input values supported by the 17bx17b and 9bx9b multipliers should be between -65536 to 65535 and -256 to 255 respectively. With this choice, we move away from the classical short and char data types supporting data values between -32768 to 32767 and -128 to 127 respectively.
I can't understand why an extra sign bit is needed on data 16b and 8b for the execution of signed operations.
Can someone enlighten me with additional information about this choice to add an extra sign bit to data 16b and 8b?
Hi there!
I'm posting here as I am having some trouble with setting up PULPissimo to be behaviourally simulated (i.e. pre synthesis) on Vivado. In order to do so, I've cloned the PULPissimo repository, then run the update ips script and finally loaded all files from ips and rtl folders into vivado project. I'll list the issues I've encountered, together with vivado logs describing the errors and warning the software detected, considering I am running a fully licensed 2020.2 version under Linux.
1) i've a huge issue with "include" files, that is the files referred by `include directives. The vivado log referring to this issue is the one named "vivado_include.log".
1.1) Initially I managed to fix some of these errors by adding the paths to the folders containing those files in "Verilog Include Files Search Paths", which is a setting that can be found by going through Project Manager -> Settings -> General(and Simulation) -> Verilog Options, but this means adding one path for every "include" error the compiler detects, so it requires a lot of work. Moreover it doesn't seem to be always working, as it didn't fix the problem when I created a new project and the log content was the same as "vivado_include.log".
2) I created another project, this time copying and including all .sv, .svh, .v files from ips and rtl PULPissimo folders, so all files are in the same folder. I had to modify the `include directives of "fpnew" IP files in order to have correct `include paths. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv, as the compiler was not able to recognize "timeunit" and "timeprecision" keywords, although it should. Then, using xilinx related scripts inside "fpga/zcu102" folder as a guideline, I created the Xilinx IPs PULPissimo requires, that is two BRAMs and two clock generators, named xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. Once I ran the behavioural simulation process, the compile phase went fine, but then the elaborate one was stopped with errors listed in "vivado_elaborate.log" file. I have to say I also read some warnings during compile phase, which details are again listed in "vivado_elaborate.log".
3) I created a new project, importing all files from ip and rtl folders. I've set some of the files referred by `include directives as "verilog header" from the files properties. Then I copied the registers.svh file inside "common_cells" folder of FPNEW ip, as the compiler was not able to find it. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv. However I still encountered errors after running behavioural simulation process, one of them referring to file riscv_alu.sv, with compiler indicating that "riscv_defines" packanot being declared.ge has not been declared. The log of this operation is inside "vivado_third_attempt.log".
All .log files are inside the attached "vivado_error_logs.zip" file.
Hope everything is clear. Thank you for your time!
