I took a look at the Near-Threshold RISC-VCore With DSP Extensions for Scalable IoT Endpoint Devices paper.
At the Dotp-Unit side, there are two 17bx17b multipliers and four 9bx9b multipliers respectively the input operands are 16b and 8b. The support of signed operations is achieved by adding a sign bit to each input operand.
The input values supported by the 17bx17b and 9bx9b multipliers should be between -65536 to 65535 and -256 to 255 respectively. With this choice, we move away from the classical short and char data types supporting data values between -32768 to 32767 and -128 to 127 respectively.
I can't understand why an extra sign bit is needed on data 16b and 8b for the execution of signed operations.
Can someone enlighten me with additional information about this choice to add an extra sign bit to data 16b and 8b?
Hi there!
I'm posting here as I am having some trouble with setting up PULPissimo to be behaviourally simulated (i.e. pre synthesis) on Vivado. In order to do so, I've cloned the PULPissimo repository, then run the update ips script and finally loaded all files from ips and rtl folders into vivado project. I'll list the issues I've encountered, together with vivado logs describing the errors and warning the software detected, considering I am running a fully licensed 2020.2 version under Linux.
1) i've a huge issue with "include" files, that is the files referred by `include directives. The vivado log referring to this issue is the one named "vivado_include.log".
1.1) Initially I managed to fix some of these errors by adding the paths to the folders containing those files in "Verilog Include Files Search Paths", which is a setting that can be found by going through Project Manager -> Settings -> General(and Simulation) -> Verilog Options, but this means adding one path for every "include" error the compiler detects, so it requires a lot of work. Moreover it doesn't seem to be always working, as it didn't fix the problem when I created a new project and the log content was the same as "vivado_include.log".
2) I created another project, this time copying and including all .sv, .svh, .v files from ips and rtl PULPissimo folders, so all files are in the same folder. I had to modify the `include directives of "fpnew" IP files in order to have correct `include paths. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv, as the compiler was not able to recognize "timeunit" and "timeprecision" keywords, although it should. Then, using xilinx related scripts inside "fpga/zcu102" folder as a guideline, I created the Xilinx IPs PULPissimo requires, that is two BRAMs and two clock generators, named xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. Once I ran the behavioural simulation process, the compile phase went fine, but then the elaborate one was stopped with errors listed in "vivado_elaborate.log" file. I have to say I also read some warnings during compile phase, which details are again listed in "vivado_elaborate.log".
3) I created a new project, importing all files from ip and rtl folders. I've set some of the files referred by `include directives as "verilog header" from the files properties. Then I copied the registers.svh file inside "common_cells" folder of FPNEW ip, as the compiler was not able to find it. Moreover I had to comment out the "`ifdef synthesis" directive in hwpe_ctrl_interfaces.sv. However I still encountered errors after running behavioural simulation process, one of them referring to file riscv_alu.sv, with compiler indicating that "riscv_defines" packanot being declared.ge has not been declared. The log of this operation is inside "vivado_third_attempt.log".
All .log files are inside the attached "vivado_error_logs.zip" file.
Hope everything is clear. Thank you for your time!
hi, I want run openPULP project in zcu104 FPGA.After i ran update_ips script,i make zcu104 under the path ../workspace/pulp/pulp/fpga.The following error occurred： ERROR: [Synth 8-439] module 'pulpissimo' not found [../workspace/pulp/pulp/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v:99] I want to know how to fix this problem,and Is it necessary to build the SDK? Can the SDK be built on the centos7 system?and how?
I'm trying to run the Hello example from "https://github.com/pulp-platform/pulp-rt-examples" in my Nexys Video FPGA using the bitstream of Pulpissimo.
Until now i'm just following the instructions from README.md file from "https://github.com/pulp-platform/pulpissimo".
I had download and install the Toolchain from pulp-riscv-gnu-toolchain as "Newlib", could someone confirm that it is not necessary install the "Linux" version of this toolchain?
Then i installed the Standard Pulp SDK from "https://github.com/pulp-platform/pulp-sdk/#standard-sdk-build"
I had some issues following the steps, most of them are related with missing steps, like configuring bashrc or some ambient variable, but i was able to solve all of them i believe. I miss some kind of step-by-step, from rtl to running example on FPGA, is it possible create something like that? I think it could be done as a new Thread in forum for the communty, it could help a lot.
I was able to generate the bitstream of Pulpissimo and configure it in Nexys Video FPGA using the JTAG-USB connection. When i run the specific OpenOCD from Pulp-SDK, the OpenOCD is able to identify the Pulpissimo processor in FPGA.
Then i compiled the Hello Example after adding the two weakly defined variables as suggested to configure core and peripherics frequencies. It was compiled with success, the ELF file was properly generate in the build directory.
My problem happen when i had try to use GDB with ELF file to load it to L2 memory of Pulpissimo, the connection between the GDB and OpenOCD looks fine, when i use the Load command it copy the elf file to memory it looks to work fine too, but when i use the Continue command it stops and never end the execution, but it print some kind of assembly commands like;
# j 1c0080ec <__rt_illegal_instr>
So i did the check with gcc in the ELF file to check the Assembly, as suspected it was printing the assembly that has some kind of error i believe, the first piece of assembly code is like that;
I am currently evaluating the use of RISC-V processors in FPGAs. Has anyone implemented a PULPino or PULPissimo on an FPGA and can you make rough statements about the resource usage?
I would appreciate any information. Thanks in advance.
Hello everyone,
Could someone please help me bypass the FLL logic ? I want to use an external clock for my design.
At the moment, I have removed the gf22_FLL instances and tried to connect soc_clk and per_clk directly to ref_clk.
Could anyone please share their experience of bypassing the FLL ? How did you handle the rest of the logic present in soc_clk_rst_gen.sv file ?
With this, I get error captured in the attachment.
I am trying to synthesize Pulpissimo with Vivado 2019.2 for nexys A7-100. I get the following errors:
Code:
[Place 30-69] Instance i_pulpissimo/pad_frame_i/padinst_bootsel/iobuf_i/IBUF (IBUF driven by I/O terminal i_pulpissimo/pad_frame_i/padinst_bootsel/iobuf_i/IO) is unplaced after IO placer
[Place 30-68] Instance i_pulpissimo/pad_frame_i/padinst_bootsel/iobuf_i/IBUF (IBUF) is not placed
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
