| Frank Gurkaynak | Introduction to Open-Source IC Design and PULP |
| Phillippe Sauter | Challenges with Basilisk and where the Future is going |
| Yichao Zhang, Diyou Shen | Physical Design Is Not Push Button |
| Lecture 1 | RTL: Refresher on SystemVerilog |
| Lecture 2 | Netlist: Turning ideas in HDL into physical gates |
| Exercise 1 | Navigating OpenROAD |
| Exercise 2 | Simulation with Verilator |
| Exercise 3 | Synthesis with Yosys |
| Exercise 4 | Floorplanning and Power Grid |
| Exercise 5 | Place & Route |
| Exercise 6 | Finishing and DRC/LVS |
| Yvan Tortorella | PULP Embedding AI at the Extreme edge of the IoT |
| Yvan Tortorella | ISA Extensions in RISC-V-Based Architectures |
| Yvan Tortorella | Multicore systems for HPC and edge AI acceleration |
| Lecture 1 | PULP Platform & PULPissimo architecture |
| Lecture 2 | Extending RISC-V cores with custom instructions |
| Lecture 3 | Integrating cooperative HW Processing Engines (HWPEs) |
| Lecture 4 | PULPissimo emulation on Zybo Z7 |
| Exercise | Accelerating FIR with Custom Hardware |